# ------------------------------------------------------------------------------
# -- HEIG-VD
# -- Haute Ecole d'Ingenerie et de Gestion du Canton de Vaud
# -- School of Business and Engineering in Canton de Vaud
# ------------------------------------------------------------------------------
# -- REDS Institute
# -- Reconfigurable Embedded Digital Systems
# ------------------------------------------------------------------------------
# --
# -- File          : comp.tcl
# -- Author        : Logisim auto-generated from comp.templ > reds@heig-vd.ch
# -- Date          : %date%
# --
# -- Context       : Logisim advanced simulator run script
# --                 Compile HDL files
# ------------------------------------------------------------------------------
# -- This file has been auto-generated by Logisim, please do not modify.
# ------------------------------------------------------------------------------


# Compile components files
# %comp_files%

# Compile top sim
if {[catch {vcom -reportprogress 300 -work work ../src/top_sim.vhdl} errmsg]} {
  puts "Compilation error: $errmsg"
  exit
}
